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Pre Silicon Validation Engineer

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Company :
Intel corporation

Location :
Hillsboro, Oregon

Expiry Date :
Thu, 17 Dec 2020 23:59:59 GMT

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Description :
Job_Description The Advanced Architecture Development Group (AADG) is part of the larger Intel’s Architecture, Graphics & Software Group (IAGS) at Intel and was formed to help create the next leap in Microprocessor Design and the future of the x86 environment at Intel. AADG is tasked with helping to solve the Innovator Dilemma when it comes to a new processor core design for Intel. This dilem can be simplified into finding the answers to questions like: What legacy components of x86 that focused on end-user desktops are really required in a world with a more cloud focused approach? If you could make any trade-off you wanted between Instructions per Cycle, Core Frequency & Power what would you do? In a world where information security is becoming more critical every-day, what should a processor core do differently? In this role, you will be responsible for validating the RTL implementation of new architecture and micro-architecture capabilities using a combination of standalone and top-level test environments as well as formal verification. You will work within a team of pre-silicon verification engineers to verify new and existing features for Intel’s next generation CPU IP, resulting in bug free final design. Responsibilities_Include,_But_Are_Not_Limited_To * Technical ownership of verification of a micro-architecture block, methodology, or otherwise significant aspect of CPU validation * Collaborate with architects, hardware engineers, and ucode engineers to understand the new features being implemented * Read and interpret technical specs and create high quality technical documentation like test plans, strategy documents and coverage plans * Plan and implement the UVM testbench, functional coverage model and assertions * Developing validation content like tools, test generators to match the complexity of new cores and be reused in pre-si and post-si * Participate in debugging failing verification tests to determine if the root cause is an error in the RTL, verification model, or the test. Fix all identified failures in the verification model * Investigating new techniques to accelerate validation of CPU hardware Qualifications Minimum Bachelors, Masters or a PhD in Electrical or Computer Engineering with 2+ years of experience in: * Computer Architecture * Digital Design * Logic Design * Data Structures * ASIC/CPU verification and functional modeling * Verification experience using SystemVerilog or Verilog and OVM/UVM for testbench development * Debugging RTL code using simulation tools Preferred_Qualifications * Projects or prior internship in ASIC/CPU verification and functional modeling * Programming in C/C++ for modeling and assembly language programming * Experience with Assertion and Functional Coverage * Scripting languages like Python/Perl Inside this Business Group Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Show moreShow less