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Principal Design Engineer Post Silicon Validation Engineer

  • Anywhere

Company :
Cadence Design Systems

Location :
San Jose, California

Expiry Date :
Mon, 26 Apr 2021 23:59:59 GMT

Apply Job :
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Description :
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Post-Silicon Validation Engineer Test Engineer This is a unique opportunity to join the rapidly growing team in the SerDes IP R & D Group at Cadence Design Systems. We are looking for a Principal Engineer who will be a key contributor to our advanced high speed SerDes IP products. This is a hands-on technical position. Main Job Tasks and Responsibilities: – Work on high speed SerDes IP bring-up, debug and automation – Conduct high speed SerDes testing and characterization – Help with infrastructure development for robust SerDes IP development and testing – Contribute to the definition and development of high speed SerDes IP product specifications – Generate test reports and application notes – Support Application Engineers during customer debug Position Requirements: – B.S./M.S. Electrical/Computer Engineering (or similar degree) – 7+ years of experience working with high speed SerDes and PHYs – Good understanding of high speed SerDes architecture – Hands on experience with high speed oscilloscopes, BERTs, VNAs, and spectrum analyzers – Experience with test chip bring-up, validation, and characterization – Must have strong debug and problem-solving skills – Experience with script-based test automation in Perl, Python, Matlab or other scripting tools – Must have strong communication and presentation skills Were doing work that matters. Help us solve what others cant.